1. Field of the Invention
The present invention relates to a driving apparatus of a display panel having a capacitive load, such as a plasma display panel of an AC driving type (hereinafter, called PDP), an electro-luminescence display (hereinafter, called EL), or the like.
2. Description of Related Art
Display apparatuses that use a flat panel of a self light emission type such as PDP, EL, or the like, are commercially available as wall type TV sets.
FIG. 1 is a schematic diagram which shows the structure of a display apparatus of that type.
As FIG. 1 shows, a PDP 10 provided as a display panel comprises two sets of row electrodes Y.sub.1 to Y.sub.n and X.sub.1 to X.sub.n. Two electrodes from each of these electrode sets together constitute a row electrode pair (X, Y) that corresponds to each row (the first row to the nth row) of one picture plane. In the PDP 10, column electrodes Z.sub.1 to Z.sub.m, which are arranged perpendicularly to the row electrode pairs are further provided so that the row electrodes and the column electrodes sandwich a dielectric layer and a discharge space which are not particularly shown in the figure. Each of the column electrodes Z.sub.1 to Z.sub.m respectively corresponds to each column (the first column to the mth column) of one picture plane. One discharge cell C.sub.(i, j) is formed in an intersecting portion between a row electrode pair (X, Y) and a column electrode Z.
The display apparatus includes a pair of row electrode driving circuits 30 and 40.
At first, the row electrode driving circuit 30 generates a reset pulse RP.sub.y of a positive voltage as shown in FIGS. 2C to 2F and applies it to the row electrodes Y.sub.1, to Y.sub.n, simultaneously. At the same time, the row electrode driving circuit 40 generates a reset pulse RP.sub.x of a negative voltage as shown in FIG. 2B, and simultaneously applies it to all of the row electrodes X.sub.1 to X.sub.n.
By applying the reset pulses RP.sub.x, and RP.sub.y simultaneously, all of the discharge cells of the PDP 10 are excited to discharge and charged particles are generated. After the discharge is terminated, a predetermined amount of wall charges are uniformly formed in the dielectric layer of all of the discharge cells (resetting stage).
After the completion of the resetting stage, a column electrode driving circuit 20 of the display apparatus generates pixel data pulses DP.sub.1 to DP.sub.n according to pixel data corresponding to the first row to the nth row of the picture plane and sequentially applies them to the column electrodes Z.sub.1 to Z.sub.m as shown in FIG. 2A. The row electrode driving circuit 30 generates a scanning pulse SP of a negative voltage in accordance with the timing of the application of the pixel data pulses DP.sub.1 to DP.sub.n and sequentially applies it to the row electrodes Y.sub.1 to Y.sub.n, as shown in FIGS. 2C to 2F.
Among the discharge cells that belong to the row electrodes to which the scanning pulse SP has been applied, a discharge occurs in those discharge cells to which the pixel data pulse of the positive voltage has been simultaneously applied. As a result the discharge, most of the wall charges are extinguished. Conversely, no discharge occurs in those discharge cells to which the scanning pulse SP has been applied but the pixel data pulse of the positive voltage is not applied. The wall charges remain unchanged in those discharge cells. In this way, the discharge cell in which the wall charges remain becomes a light-emission discharge cell and the discharge cell in which the wall charges have been extinguished becomes a non-light emission discharge cell (addressing stage).
After the addressing stage has finished, the row electrode driving circuits 30 and 40 continuously apply a sustaining pulse IP.sub.y of the positive voltage to each of the row electrodes Y.sub.1 to Y.sub.n as shown in FIGS. 2C to 2F. The row electrode driving circuits 30 and 40 also continuously apply a sustaining pulse IP.sub.x of the positive voltage to each of the row electrodes X.sub.1 to X.sub.n at a timing deviated from the timing of the application of the sustaining pulse IP.sub.y, as shown in FIG. 2B.
For a period of time during which the sustaining pulses IP.sub.x and IP.sub.y are alternately applied, the discharge light emission is repeated by the light emission discharge cells in which the wall charges remain, thereby the light emitting state is sustained (sustaining discharge stage).
A drive control circuit 50 is provided shown in FIG. 1. Based on the timing of a supplied video signal, the drive control circuit 50 generates various switching signals for generating various driving pulses as shown in FIG. 2. The generated switching signals are supplied to the column electrode driving circuit 20 and the row electrode driving circuits 30 and 40.
The column electrode driving circuit 20 and the row electrode driving circuits 30 and 40 generate various driving pulses shown in FIGS. 2A to 2F in accordance with the switching signals supplied from the drive control circuit 50.
FIG. 3 is a diagram showing a driving pulse generating circuit which is provided in the row electrode driving circuit 30 and generates the reset pulse RP.sub.y and sustaining pulse IP.sub.y.
As FIG. 3 shows, the driving pulse generating circuit has a capacitor C1 whose one end is connected to a PDP grounding potential V.sub.s as a grounding potential of the PDP 10. The driving pulse generating circuit also includes a plurality of switching elements S1 through S4 which are arranged in the manner as shown in the figure.
The switching element S1 is in an OFF state for a period in which a switching signal SW1 of the logic level "0" is supplied from the drive control circuit 50. When the logic level of the switching signal SW1 is equal to "1", the switching element S1 is in a connection state and an electric potential generated at the other end of the capacitor C1 is applied onto a line 2 via a coil L1 and a diode D1. The capacitor C1, consequently, starts discharging and an electric potential generated by the discharge is applied onto the line 2.
The switching element S2 is in the OFF state for a period in which a switching signal SW2 of the logic level "0" is supplied from the drive control circuit 50. The switching element S2 is in the connection state when the logic level of the switching signal SW2 is equal to "1" and the potential on the line 2 is applied to the other end of the capacitor C1 via a coil L2 and a diode D2. That is, the capacitor C1 is charged by the potential on the line 2.
The switching element S3 is in the OFF state for a period in which a switching signal SW3 of the logic level "0" is supplied from the drive control circuit 50. When the logic level of the switching signal SW3 is equal to "1", the switching element S3 is in the connecting state and a positive side terminal potential V.sub.c of a DC power source B1 is applied onto the line 2. The PDP grounding potential V.sub.s is applied to a negative side terminal of the DC power source B1.
The switching element S4 is in the OFF state for a period in which a switching signal SW4 of the logic level "0" is supplied from the drive control circuit 50. When the logic level of the switching signal SW4 is equal to "1", the switching element S4 is in the connection state and the PDP grounding potential V.sub.s is applied onto the line 2.
The line 2 is connected to the row electrodes Y in the PDP 10 that has a load capacitance C0. In the row electrode driving circuit 30, the circuits as shown in FIG. 3 are provided for n systems that correspond to the number of row electrodes Y.sub.1 to Y.sub.n.
FIGS. 4A to 4G are diagrams showing timings of the switching signals SW1 to SW4 which are supplied to the row electrode driving circuit 30 shown in FIG. 3 from the drive control circuit 50 so as to generate the sustaining pulse IP.sub.y as shown in FIGS. 2C to 2F onto the line 2.
As shown in FIGS. 4A to 4D, only the switching signal SW4 among the switching signals SW1 to SW4 has the logic level "1" at first. So, the switching element S4 is in the connection state and the PDP grounding potential V.sub.s is applied onto the line 2. During this period, the potential on the line 2 is equal to the PDP grounding potential V.sub.s, that is, 0 [V].
When the switching signal SW4 is subsequently turned to the logic level "0" and the switching signal SW1 is turned to the logic level "1", only the switching element S1 is in the connection state, so that the charges accumulated in the capacitor C1 are discharged. Consequently, a current transiently flows into the coil L1 in such a form as shown in FIG. 4E. The current flows into the PDP 10 through the diode D1, switching element S1, and line 2 to charge the load capacitance C.sub.O, so that the potential on the line 2 gradually increases as shown in FIG. 4G.
When the switching signal SW1 is switched to the logic level "0" and the switching signal SW3 is switched to the logic level "1", only the switching element S3 is in the connecting state and the positive side terminal potential V.sub.c of the DC power source B1 is applied onto the line 2. Therefore, the potential on the line 2 is fixed to V.sub.c for this period of time, as shown in FIG. 4G.
When the switching signal SW2 is switched to the logic level "1" and the switching signal SW3 is switched to the logic level "0", only the switching element S2 enters into the connection state and a negative current transiently flows in the coil L2 in the form as shown in FIG. 4F. The load capacitance C.sub.O of the PDP 10 charged as mentioned above is discharged and the current flows into the capacitor C1 via the line 2, coil L2, diode D2, and switching element S2, to be retrieved therein. Consequently, the potential on the line 2 decreases gradually as FIG. 4G shows.
By the above mentioned operations, the sustaining pulse IP.sub.y of the positive voltage as shown in FIG. 4G is applied onto the line 2.
With the circuit having the structure shown in FIG. 3, there however is a problem that the circuit scale becomes large because of the necessity of the use of the four switching elements S1 to S4.
It is conceivable to implement each of the switching elements S1 to S4 by an MOS transistor. Even in such a case, a dedicated power source has to be prepared for the switching and driving of the switching elements S1 to S3 among the switching elements S1 to S4. This is because, the MOS transistors cannot be switched directly by the switching signals SW1 to SW3 since the electric potential which is applied across each of the switching elements S1 to S3 is in a floating state for each of the switching signals SW1 to SW3 as shown in FIG. 3.
For example, when the switching element S1 is formed by an MOS transistor, therefore, it actually has such a structure as shown in FIG. 5.
Specifically, an MOS transistor Q is connected between the diode D1 and the line 2 shown in FIG. 3 and, to allow the MOS transistor Q to perform the switching operation in response to the switching signal SW1, photocoupler PC, power source B2, and driver DV are further necessary. When the switching signal SW1 has the logic level "1", the driver DV supplies an electric potential V.sub.DD on the high potential side in the power source B2 to a gate terminal of the MOS transistor Q. When the switching signal SW1 has the logic level "0", an electric potential V.sub.0 on the low potential side in the power source B2 is supplied to the gate terminal. The potential V.sub.0 is always applied to a drain terminal of the MOS transistor Q. The photocoupler PC electrically insulates the logic level of the switching signal SW1 and relays it to the driver DV.
When the switching elements S1 to S3 are implemented by the MOS transistors in the construction shown in FIG. 3 as mentioned above, an additional circuit as shown in FIG. 5 is necessary. This causes problems that the circuit scale becomes large and the operating speed decreases.